In many data communication applications, Serializer and De-serializer (SerDes) devices facilitate the transmission between two points of parallel data across a serial link. Data at one point is converted from parallel data to serial data and transmitted through a communications channel to the second point where it received and converted from serial data to parallel data.
At high data rates, frequency-dependent signal loss from the communications channel (e.g., the signal path between the two end points of a serial link) as well as signal dispersion and distortion can occur. As such, the communications channel, whether wired, optical, or wireless, acts as a filter and might be modeled in the frequency domain with a transfer function. Correction for frequency dependent losses of the communications channel, and other forms of signal degradation, often requires signal equalization at a receiver of the signal. Equalization through use of one or more equalizers compensates for the signal degradation to improve communication quality.
In many data communication applications generating one or more different source clock signals, a clock and data recovery circuit (CDR) is employed to recover an input data clock signal, and generate clock signals having a known phase alignment. For example, SerDes devices that facilitate the transmission between two points of parallel data across a serial link often must generate multiple clock signals to support various standards. Bang-bang Phase Detectors (BBPD) are employed in applications that require detection and phase alignment of these different clock domain sources.
An eye pattern, also known as an eye diagram (or “eye”), represents a digital data signal from a receiver that is repetitively sampled and applied to the vertical input (axis), while the horizontal input (axis) represents time as a function of the data rate. The eye diagram allows for evaluation of the combined effects of channel noise and inter-symbol interference on the performance of a baseband pulse-transmission system, and the input data eye is the synchronized superposition of all possible realizations of the signal of interest viewed within a particular signaling interval (referred to generally as the data eye), which for convenience might be referred to generally as a unit interval or “UI”. A data slicer (i.e., a Data Latch) in a SerDes device is used for digitizing an analog signal in the serial data receiver. Precision of the latch threshold has substantial impact on performance (e.g., error rate, jitter tolerance) of the SerDes device.
A bang-bang, or Alexander-type, phase detector is the most commonly used phase detector in SerDes receivers for clock and data recovery. In a decision feedback equalization (DFE)-based receiver often employed in a mixed-signal SerDes device, the required separation between the data sample (I) and the transition sample (Q) to get proper eye centering (and hence maximum horizontal margin) might be different from the nominal value (e.g., 0.5 T, where T is the transition period (also the sampling period for the data slicer). This asymmetry in the sampled eye leads to loss of horizontal margin in the eye and, hence, degraded bit error rate (BER) performance.
The classical bang-bang phase detector settles to the transition sampling point, but the DFE output inner eye is typically not fully centered, leading to a loss in horizontal margin and a degraded BER performance.